The transition from analog to digital offers many advantages to help maintain the quality of the video signal throughout the facility. Once the video signal is within the digital domain, it does not suffer from many of the analog phenomena that can affect signal quality. By digitizing a high-quality video signal, many of the analog defects can be removed from the signal. However, some familiar engineering practices need to change in order to cope with a signal in the digital domain.
For example, the serial digital interface (SDI) is robust, but beyond a certain point, the integrity of the transmitted signal cannot be guaranteed, and the data will likely fall off the digital cliff. In SDI, the clock is embedded within the data- stream. If the receiving equipment is unable to recover the clock, it is unable to recover the video data, and the picture cannot be displayed. Unfortunately, unlike analog, where degradation of the signal occurs gradually, in a digital system, the loss of the picture happens almost instantaneously. Therefore, the job of the engineer within a digital television facility is to maintain the health of the signal to prevent it from falling off the digital cliff.
To qualify installation, specific digital stress testing signals can be applied to the system from a suitable test pattern generator. The SDI Check Field is a specialized test signal that contains two parts, as shown in Figure 1.
One component of the SDI Check Field tests equalizer operation by generating a sequence of 19 zeros followed by a one (or 19 ones followed by one zero). This occurs about once per field as the scrambler attains the required starting condition and will persist for the full line until terminated by the EAV packet. This sequence produces a high DC component that stresses the analog capabilities of the equipment and transmission system handling the signal. The other part of the SDI Check Field signal is designed to check phase-locked loop performance with an occasional signal consisting of 20 zeros followed by 20 ones. This provides a minimum number of zero crossings for clock extraction.
These types of tests are useful while proving the conformance of your digital system or performing out-of-service testing. But once the installation is complete, how can you monitor the health of your system to ensure that signals do not reach the digital cliff or that a piece of equipment isn’t close to failing?
Figure 2. Various waveform monitors and SDI analyzers can provide status reports of the EDH condition and can log errors. Click here to see an enlarged diagram.
Error detection and handling (EDH) is based on inserting cyclic redundancy code (CRC) calculations for each field of video within the vertical ancillary data area. Separate CRCs for the full field and active picture, along with status flags, are sent with the other serial data through the transmission system. The CRCs are recalculated at the deserializer. If the calculated CRC values are not identical to the transmitted values, an error is indicated.
Therefore, this method can be used for in-service monitoring of the SDI signal. Most video equipment now supports embedding of EDH within the vertical ancillary data area. Various waveform monitors and SDI analyzers can provide status reports of the EDH condition and can log errors, as shown in Figure 2.
Typical error detection data will be presented as errored seconds over a period of time and time since the last errored second. If the monitoring equipment reports that EDH errors are occurring often, this is an indication that the SDI signal is getting close to the edge of the digital cliff, and the signal path should be investigated further to identify the problem.
Figure 3. The eye diagram is constructed by overlaying portions of the sampled data stream until enough data transitions are available to produce the 3-eye display as shown here. Click here to see an enlarged diagram.
To isolate these types of problems within a digital system, a waveform monitor with the ability to display an SDI eye diagram is required. For accurate measurement, it is important to use a short cable length of high-quality cable between the monitor and test point. The eye diagram is constructed by overlaying portions of the sampled datastream until enough data transitions are available to produce the 3-eye display as shown in Figure 3.
On some instruments, it is also possible to correlate the eye display to data word boundaries (10-word for SD and 20-word for HD). This feature is useful for detecting jitter patterns related to parallel-to-serial conversion.
Figure 4. The jitter display shown here plots peak-to-peak jitter versus time related to video line and field rates. This allows jitter to be characterized related to the video signal timing. Click here to see an enlarged diagram.
A serial receiver determines if the signal is a high or a low in the center of each eye, thereby detecting the serial data. As noise and jitter in the signal increase through the transmission channel, they can close the eye, reducing the usefulness of the received signal.
SMPTE standards specify requirements for the launch amplitude, jitter, overshoot and rise/fall time of the signal, as specified in Table 1.
Signal amplitude is important because of its relation to noise and because the receiver estimates the required high-frequency compensation (equalization) based on the half-clock-frequency energy remaining in the received signal. Incorrect amplitude at the sending end could result in an incorrect equalization being applied at the receiving end, causing signal distortion.
The rise and fall times are determined between the 20 percent and 80 percent amplitude points as defined in Table 1. Incorrect rise time could cause signal distortions, such as ringing and overshoot, or, if too slow, it could reduce the time available for sampling within the eye. Overshoot of the rising and falling edge must not exceed 10 percent of the waveform. Overshoot could be the result of incorrect rise time but will more likely be caused by impedance discontinuities or poor return loss at the receiving or sending terminations.
Jitter is seen in the eye diagram as a horizontal thickening of the trace. As jitter increases, the opening of the eye shrinks until the receiver can no longer decode the data. Jitter is measured in unit intervals (UI), where 1UI is equivalent to reciprocal of the clock period: 3.7ns for SD and 673.4ps for HD. The effect of jitter on the system is also dependent on the frequency of the jitter. SMPTE defines different frequency bandwidths for measuring jitter. Timing jitter provides an overall measure of the jitter present within the transmitted signal, while alignment jitter isolates jitter components that adversely affect the receiver’s ability to recover the data. The jitter display in Figure 4 plots peak-to-peak jitter versus time related to video line and field rates. This allows jitter to be characterized related to the video signal timing. Many jitter-related problems are the result of genlocking reference jitter transferred into the serial system. This type of jitter is typically between 20Hz and several hundred Hz. The phase detection process used by genlock systems also can add noise that contributes to jitter in the 10Hz to 1kHz range. By using the appropriate bandwidth-limiting filter, specific jitter components can be included or rejected from the jitter measurement.
The eye and jitter displays of the waveform monitor are the tools of choice for measuring the performance of a digitally transmitted signal. EDH, if implemented correctly in a system, can help monitor critical signal paths and warn of potential problems in the system. The key to a properly maintained system is a well-designed facility where cable type, cable length and correct termination of the equipment are continually maintained.
Michael Waidson is an application engineer for Tektronix.
